1. Field of the Invention
The present invention relates to an embedded semiconductor device substrate having a semiconductor device buried in an insulating resin layer of a printed wiring board, and a method of producing the same.
2. Description of the Related Art
In recent years, the semiconductor package having a semiconductor device mounted therein has been continuously reduced in size and weight. Therefore, there has been increasing adopted a structure in which an electrode portion of a semiconductor package is formed into an area array, such as BGA (Ball Grid Array) and CSP (Chip Scale Package).
Furthermore, not only a two-dimensional size reduction such as the BGA and CSP, but also a multi chip package in which a plurality of semiconductor devices are stacked in a single package has been proposed such as disclosed in Japanese Patent Application Laid-Open No. H11-3970.
On the other hand, in addition to such size reduction of semiconductor packages, an embedded semiconductor device substrate having a semiconductor device buried inside of a printed wiring board has been proposed such as disclosed in Japanese Patent Application Laid-Open No. H09-321408. In the embedded semiconductor device substrate disclosed in Japanese Patent Application Laid-Open No. H09-321408, a semiconductor device having stud bumps formed thereon is mounted in a recessed portion formed beforehand on a printed wiring board, and an insulating layer is then formed so as to cover the semiconductor device.
However, in the embedded semiconductor device substrate described in Japanese Patent Application Laid-Open No. H09-321408, since a routering is necessary for forming a recessed portion in a printed wiring board, which increases the processing time remarkably. In addition, in order to bury a semiconductor device, it is necessary to form a holding surface for holding the semiconductor device at a bottom of the recessed portion, and an insulating layer is needed for the holding surface. In consequence, the thickness of the embedded semiconductor device substrate having the semiconductor device varied therein becomes very large, which makes the size reduction difficult.
So, there has been proposed a method which does not form a recessed portion beforehand in a printed wiring board but buries a semiconductor device during production of a printed wiring board to thereby produce an embedded semiconductor device substrate, in Japanese Patent Application Laid-Open No. 2004-335641. The production method disclosed therein will be explained with reference to FIGS. 10A to 10F.
First, as shown in FIG. 10A, a semiconductor device 101 is mounted through an insulating epoxy resin 104 on a Cu foil 103. Next, as shown in FIG. 10B, a prepreg material 105 is disposed at such a location that an opening 105a of the prepreg materiel 105 contains the semiconductor device 101. The prepreg material 105 has approximately the same thickness as the thickness of the semiconductor device 101, and the opening 105a having a shape corresponding to the shape of the semiconductor device 101 is formed with a punching press. In addition, on the prepreg material 105, there is put an RCC (Resin Coated Cupper) material 107 having an epoxy resin 106 as an insulating resin coated on a Cu foil 103a. The Cu foil 103, prepreg material 105, and RCC material 107 (epoxy resin 106/cupper foil 103a) are disposed by stacking in this way, and are subjected to thermocompression bonding in a vacuum atmosphere as shown in FIG. 10C.
Next, as shown in FIG. 10D, a part of the Cu foil 103a corresponding to an electrode portion 102 on the semiconductor device 101 is removed by ordinary etching to form a hole portion. Then, a part of the epoxy resin 106 which is exposed via the hole portion is removed by a laser such as a CO2, YAG, or excimer laser to form an opening 108, whereby the electrode portion 102 of the semiconductor device 101 is exposed therethrough. Next, as shown in FIG. 12E, while a Cu layer 103b is formed on the entire surface by plating, the opening 108 is filled with the Cu layer 103b. 
Subsequently, a resist material is coated on the Cu layer 103b, and a wiring pattern is formed in an exposure step through a mask and a development step, so that the embedded semiconductor device substrate having the semiconductor device 101 integrated therein as shown in FIG. 10F is obtained.
In the embedded semiconductor device substrate disclosed in Japanese Patent Application Laid-Open No. 2004-335641 above, by forming an opening accurately by use of a laser, electrodes of a semiconductor device are exposed outside. Furthermore, by etching a Cu layer formed on a printed wiring board by use of a mask, a wiring pattern connected to the electrodes is formed. Hence, there is required an etching accuracy of such an extent as to surely connect the electrodes of the semiconductor device and the wiring pattern on the printed wiring board to each other.
On the other hand, since a large number of semiconductor devices are produced from a single semiconductor wafer, there are differences between individual semiconductor devices obtained therefrom, and there are positional errors between the individual semiconductor devices also with regard to electrode positions. Furthermore, there will be necessarily generated a mounting error within a predetermined range in the mounting position of a semiconductor device to a printed wiring board. Therefore, there is generated a displacement with respect to a design position between the patterning position of a wiring pattern, and the position of an electrode of a semiconductor device. Generally, in prospect of this displacement, the patterning using a mask is made so as to provide a pattern shape with a predetermined amount of margin.
Nevertheless, as the pitch of electrodes of a semiconductor device is reduced, it becomes impossible to take a sufficient margin to avoid interference with an adjacent wiring pattern. That is, it becomes difficult to allow the above described errors when mounting semiconductor devices to a printed wiring board and positional errors of electrodes between individual semiconductor devices, by means of a margin of a pattern shape. Thereby, the electrodes of the semiconductor devices and the wiring on the printed wiring board will not be connected. Such a situation becomes significant as the pitch between electrodes of a semiconductor device is reduced, and it is believed that it will become a more serious problem in the future.